1. Field of the Invention
The present invention relates to a sampling clock generating circuit for generating a sampling clock which is used for A-D conversion of various kinds of video signals.
2. Description of the Prior Art
FIG. 1 is a block diagram of a conventional sampling clock generating circuit. In the figure, indicated by 4 is a phase comparator for comparing the phase of a signal which is produced through the frequency demultiplication of the sampling clock with the phase of the horizontal sync signal so as to produce an error signal, 5 is a low-pass filter for smoothing the error signal, 6 is a voltage-controlled oscillator varying its oscillation frequency in response to the control voltage level, and 7 is a programmable frequency demultiplier which demultiplies the sampling clock frequency at a preset dividing ratio N.
Next, the operation of the circuit will be explained.
The sampling clock is demultiplied at a preset dividing ratio N in the programmable frequency demultiplier 7. The programmable frequency demultiplier 7 produces an output signal, which is compared in phase with the horizontal sync signal by the phase comparator 4, which then produces an error signal indicative of the phase difference between the two signals. The error signal is smoothed by the low-pass filter 5, and the resulting signal becomes the control voltage for the voltage-controlled oscillator 6. The voltage-controlled oscillator 6 varies its oscillation frequency in response to the control voltage. This circuit arrangement of a phase-locked loop (PLL) provides a sampling clock which is equal in phase with the horizontal sync signal and has a frequency N times the horizontal sync frequency.
It is difficult to design a voltage-controlled oscillator which operates stably in a wide frequency range. Therefore, in situations where the sampling clock is required to have a wide frequency range, either several voltage-controlled oscillators having various frequency ranges are selected by switching, or the sampling clock is extracted out of an intermediate stage of a programmable counter.
The conventional circuit as described above depends, for the stability of the sampling clock, largely on the stability of the externally-supplied horizontal sync signal. Thus, such sampling clocks can properly sample only video signals having stable horizontal sync signals.
In addition, there is another problem with conventional sampling clocks in that it is difficult to construct a stable PLL since different horizontal sync frequencies need different comparison frequencies.